The present invention relates to a power supply unit, and relates to, for example, a technique effective in application to a switching power supply unit that converts a high voltage into a low voltage.
For example, Patent document 1 (Japanese patent translation publication No. 2005-520475) describes a multiphase buck converter comprising: n inductors in parallel connection with a common capacitor; n output switching devices coupled to these inductors, respectively; n phase output devices that drive these output switching devices by PWM control, respectively; and a phase control device that supplies a common control signal to each of the phase outputting devices (FIG. 1). The phase control device supplies the n phase output devices with a phase timing signal such as a triangular waveform, and a PWM control signal for determining a PWM duty. This triangular waveform is determined by a voltage level different in each of the n phase output devices, and whereby a timing signal having n phases that differ for each of the n phase output devices is generated (FIG. 12d). Each of the n phase output devices drives, within its own phase, a corresponding output switching device by a PWM duty based on the above-described PWM control signal.
Moreover, Patent document 2 (Japanese patent laid-open No. 2007-135390) describes a multiphase converter comprising: n inductors in parallel connection with a common capacitor; n transistor pairs coupled to the inductors, respectively; n phase ICs that drive the transistor pairs by PWM control, respectively; a control IC that supplies a common control signal to each of the phase ICs (FIG. 1, FIG. 2). The control IC generates a clock signal, a phase-out signal (pulse signal), an error amplifier signal for determining the PWM duty, and the like. The first phase IC receives the phase-out signal as a phase-in signal from the control IC, delays it by one clock, and then outputs it to the second phase IC as a phase-out signal. The second phase IC receives the phase-out signal from the first phase IC as a phase-in signal, delays it by one clock, and then outputs it to the third phase IC as the phase-out signal. The following phase ICs performs the same operations, and finally, a phase-out signal from the n-th phase IC is fed back as the phase-in signal of the control IC. Each of the phase ICs drives a corresponding transistor pair by a PWM duty corresponding to the error amplifier signal, based on the timing of its own phase-in signal.
Moreover, Patent document 3 (Japanese patent laid-open No. 2008-17620) describes a semiconductor device, wherein a power MOSFET, a drive circuit that drives the same, and a control circuit that transmits a switching control signal to the driver circuit are incorporated into one package (FIG. 1, FIG. 2). This semiconductor device employs a peak current control method, in which the PWM duty is determined by the result of comparison between an error amplifier signal (criterion level) reflecting a detection voltage from an external capacitor coupled to the power MOSFET and a signal (ramp signal) obtained by detecting a current flowing through the power MOSFET and converting it into a voltage (FIG. 8, FIG. 9). Moreover, this semiconductor device contains an oscillator circuit, and can share the output of this oscillator circuit, the above-described error amplifier signal, and the like with other semiconductor devices via external terminals (FIG. 17).
Moreover, non-Patent Document 1 (“ISL6327 Data Sheet”, [online], [Searched on Feb. 12, 2008], Internet <URL: http://www.intersil.com/data/fn/FN9276.pdf>) describes a six-phase buck converter comprising: six inductors in parallel connection with a common capacitor; six transistor pairs coupled to the inductors, respectively; six driver ICs that drive the transistor pairs, respectively, by PWM control; and a control IC that controls each of the driver ICs. The control IC includes: six pairs (of positive side and negative side) of external input terminals for detecting currents flowing through the six inductors, respectively; six external output terminals for supplying a PWM signal having a different phase to six driver ICs, respectively; a plurality of external input terminals for externally setting the setting voltage of the common capacitor; and the like.